1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a hemispherical silicon grain (HSG) layer on a capacitor electrode so as to increase the surface area.
2. Description of Related Art
A capacitor generally includes two electrodes and a dielectric layer between these two electrodes. In order to increase capacitance, either the dielectric thickness is reduced or the electrode area is increased. One of methods of increasing the electrode area is to use a polysilicon layer with a selective HSG layer on its top surface as a lower electrode. Since the selective HSG layer includes a lot of small hemispherical structures, the total area is naturally increased so that the capacitance is accordingly increased. However, the selective HSG layer is not easily formed on the polysilicon layer. The selective HSG layer is usually first formed on an amorphous silicon layer, and an annealing process is performed to transform the amorphous silicon layer into the polysilicon layer.
FIGS. 1A-1E are cross-sectional views of a portion of a semiconductor substrate, schematically illustrating conventional fabrication processes for forming a lower electrode of a capacitor with a HSG layer. In FIG. 1A, a dielectric layer 102 is formed over a substrate 100. An opening 104 is formed in the dielectric layer 102 to expose a portion of the substrate 100.
In FIG. 1B, an amorphous silicon layer 106 with a thickness of about 8000 .ANG. is formed over the substrate 100 so that the opening 104 is filled also. The amorphous silicon layer 106 is doped with a dopant of, for example, phosphorus or arsenic so as to increase the conductance. The dopant concentration is about 10.sup.15 1/cm.sup.3. The amorphous silicon layer 106 is formed by chemical vapor deposition (CVD). However, the amorphous silicon layer 106 has a very long formation time of about 12-16 hours.
In FIG. 1C, the amorphous silicon layer 106 is patterned and becomes an amorphous silicon layer 106a that fills the opening 104 and covers a layer 102 around the opening 104. A portion of the amorphous silicon layer 106a remains exposed.
In FIG. 1D, a selective HSG layer 110 is formed over a peripheral surface of the exposed portion of the amorphous silicon layer 106a. Since the selective HSG layer 110 includes a lot of hemispherical silicon grains, the total surface area increases. This can increase the surface area of a lower electrode of a capacitor formed later.
In FIG. 1E, an annealing process is globally performed so as to transform the amorphous silicon layer 106a into a polysilicon layer 106b. The selective HSG layer 110 and the polysilicon layer 106b form together as a lower electrode 112. However, due to the annealing process, an oxide layer 114 may form at the interface between the lower electrode 112 and the substrate 100. This oxide layer 114 increases contact resistance of the lower electrode 112 to the substrate 100, which increased contact resistance worsens performance.
Another conventional method for fabricating a lower electrode of a capacitor uses a polysilicon base layer as a base of the lower electrode, like the amorphous silicon layer 106a in FIG. 1C. The exposed surface of the polysilicon base layer is implanted with ions to form a doped polysilicon bas layer with an amorphous surface layer on its exposed surface. A selective HSG layer like the selective HSG layer 110 of FIG. 1D is formed over the exposed surface of the doped polysilicon base layer. This alternative conventional method can reduce the fabrication time because it takes shorter time to form the polysilicon base layer. The doped polysilicon base layer can also prevent the oxide layer 114 of FIG. 1D from occurring. However, the implanted ions on the exposed surface of the polysilicon base layer has an insufficient concentration distribution so that quality of the grain structure of the selective HSG layer on the doped polysilicon base layer is poor. Moreover, during the formation of the selective HSG layer, the amorphous surface layer of the doped polysilicon base layer may be gradually re-crystallized, and transformed into polysilicon so that the selective HSG layer is not formed.
The conventional methods described above mainly have two issues. If the lower electrode is formed by forming the HSG layer 110 on the amorphous silicon layer 106a, the contact resistance to the substrate is increased. If the lower electrode is formed by forming the HSG layer on the doped polysilicon base layer, the HSG layer may be poor in quality or may even not be formed.